MATCSI
31: APPLIED MATHEMATICS - I
Hours per week :4
I.A
Marks: 25
Total Lecture Hours: 48
Exam Marks: 100
1. NUMERICAL ALGORITHMS
12
Hrs
Approximations and Errors - Significant Figures, Accuracy and Precision,
Round Off and Truncation Errors. Algorithms to Compute Roots of Equations -
Bisection Method, Newton Raphson Method, Method of False Position.
Algorithms to Solve Linear Algebraic Equations - Gauss Elimination, Gauss
Jordan, Gauss Seidel, LU Decomposition. Algorithms to Solve Ordinary
Differential Equations - Euler Method and Modifications, Runge Kutta II and
IV Order Methods.
2. FOURIER
SERIES AND FOURIER TRANSFORMS
12 Hrs
Periodic Functions - Elle's Formula, Fourier Series of Even and Odd
Functions, Fourier Series of Functions of Arbitrary Period, Half Range
Expansion, Practical Harmonics. Definition of Fourier Transform, Cosine and
Sine Transforms, Inverse Transforms, Convolution, Applications of Fourier
Transforms.
3. PROBABILITY
9
Hrs
Axioms and Models, Conditional Probability, Baye's Rule - Examples. Random
Variables - Simple Examples, Discrete and Continuous Random Variables,
Jointly Distributed Random Variables, Distributions of Random Variables -
Examples. Expectation - Moments. Conditional Distributions and Conditional
Expectations. Stochastic Process - Bernoulli and Poisson Process.
4. STATISTICAL INFERENCE 9
Hrs
Random Sampling, Sampling Distributions, Parameter Estimation and Hypothesis
Testing, Regression, Correlation and Analysis of variance.
5. MARKOV CHAINS
6 Hrs
Continous Parameter and Discrete Parameter Markov Chains. Concept of a
Queue, The M/G/I and M/M/I Queuing Systems, Simple Analysis - Examples.
Text Books:
1. Steven C. Chapra and Raymond P.Canale, Numerical Methods for Engineers,
McGraw-Hill, 3rd Ed., 1998.
2. Grewal B.S., Higher Engineering Mathematics.
3. Miller, Freund and Johnson, Probability and Statistics for Engineers, 4th
Ed., PHI, 1990
4. K.S. Trivedi, Probability, Statistics with Reliability, Queuing and
Computer Science Applications, PHI, 1988.
Reference Books
1. V.Raj ararnan, Computer Oriented Numerical Methods, 2nd Ed., PHI, 1992.
2. Krishna Murthy and Sen, Numerical Algorithms, AEWP, 1991
3. McCormick and Salvadori, Numerical Methods in FORTRAN, PHI, 1992
4. L.Kleinrock ,Queuing Theory ,Vol I and II.
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CSI
32 : DISCRETE MATHEMATICAL STRUCTURES
Hrs Per Week :04
I.A.Marks
:25
Total Lecture Hrs :48 Exam.Marks:100
1. FUNDAMENTALS
10 Hrs
Sets and subsets, Operations on sets, Counting - Permutations, Combinations,
Pigeonhole principle, Recurrence relations.
2. LOGIC
6 Hrs
Propositions and logical operations, Conditional statements, Methods of
proof, Mathematical Induction.
3. RELATIONS AND FUNCTIONS
16 Hrs
Product sets and partitions, Relations and Digraphs, Paths in relations and
digraphs, Properties of relations, Equivalance relations, Computer
representation, Manipulation of relations, Transitive closure and Warshall's
algorithm.Functions - Functions for computer science, Permutation functions,
Growth of functions.
4. ORDER RELATIONS AND STRUCTURES
8 Hrs
Partially ordered sets, External elements, Lattices, Finite Boolean
Algebras.
5 SEMIGROUPS AND GROUPS
8Hrs
Semigroups, Products and Quotients of Semigroups, Products and Quotients of
Groups.
Text Book
1. Bernard Kolman, Robert C Busby, Sharon Ross, Discrete mathematical
structures, Third Edition,PHI 1997. ( Chapters 1.1 to 1.3, 2, 3.1 to 3.3,
3.5, 4, 5, 7.1 to 7:5, 9 )
Reference Books 1. Lipschutz, Discrete Mathematics, Schauni's Series,
2. R Johnsonbaugh, Discrete Mathematics, Revued edition Macmillan
International,1989.
3. C L Liu, Elements of Discrete Mathematics, McGraw Hill 1986.
4. Trembly & Manohar, Discrete Mathematics with application to Computer
Science, McGraw Hill, 1988.
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CSI 33 : DATA STRUCTURES WITH C
Hours per week :4 I.A
Marks : 25
Total Lecture Hours: 48
Exam Marks: 100
1. Review of structures and pointers, Introduction to special features of C
8 Hrs
Register variables, Bitwise operators, Bit fields, Enumerations, Command
line parameters, Macros, Preprocessor statements. Dynamic Memory Allocation.
Files.
2. THE STACK
6 Hrs
Definition and Examples, Representation of stacks in C, Evaluation of
Postfix expression, Conversion from Infix to postfix.
3. RECURSION
4Hrs
Recursive
definition and processes, Recursion in C, Writing recursive programs,
Efficiency of Recursion, GCD, Fibonacci, Binomial coefficients and Tower of
Hanoi problems.
4. QUEUES AND LISTS
8 Hrs
The Queue and its sequential representation. Linked lists, Lists in C, Other
list structures.
5. TREES 8
Hrs
Binary
trees, Binary tree representations, Trees and their Applications.
6. SORTING
8 Hrs
General background, Quick Sort, Binary tree sorts, Heap sort -Heap as
priority queue, Sorting using a Heap, Heap sort procedure. Insertion Sorts -
Simple Insertion, Shell sort ,Address calculation sort, Radix sort.
7. SEARCHING
6 Hrs
Basic search techniques- Algorithmic notation, Sequential Searching,
Searching an Ordered Table, Binary Search. Interpolation Search, Tree
Searching - Binary Search Tree Insertions and Deletions. Hashing - Resolving
Hash Clashes by Open Addressing.
Text
Book:
1. Yedidyah Langsam, Moshe J Augenstein & Aaron M Tenenbaum, Data
Structures using C and C++,2nd Ed., PHI, 1997. ( Chapters 2, 3.1 to 3.3,
3.5, 4.1 to 4.3, 4.5,5.1,5.2, 5.5, 6.1, Selected Portions from 6.2 to 6.5,
7.1,Selected Portions from 7.2 and 7.4)
2. E. Balaguruswamy, Programming in ANSI C, 2nd Ed., TMH,1998 ( Chapters 11,
12 and Selected portions from 13, 14 and Appendix I)
Reference Books:
1. Robert L Kruse, Data Structures and Program Design using C, PHI. 2.
Trembly & Sorenson, Data Structures, McGraw Hill.
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CSI
34 : LOGIC DESIGN
Hours per week :4
I.A Marks: 25
Total Lecture Hours :48 Exam
Marks: 100
Note: Use of IEEE/ANSI standard logic symbols is recommended in
addition to conventional symbols (Ch. 3-15; 5-10; 6-18; 7-10; 7-23; 9-10; of
Tocci and Widmer book)
1.
SIMPLIFICATION OF BOOLEAN FUNCTIONS
(10
Hrs)
The K- map method (up to 4 variables), SOP and P0S simplification, NAND and
NOR implementation, don't care conditions. Quine-MeCluskey tabulation method
(5-variables, Decimal notation) - determination and selection of prime
implicants.
2. COMBINATIONAL LOGIC
6 Hrs
Design procedure, design of adders, subtractors, and code converters.
Analysis procedure, multi level NAND and NOR circuits, Ex-OR and equivalence
functions.
3. COMBINATIONAL LOGIC WITH MSI AND LSI
8
Hrs
Application of typical TTL IC components like Binary Parallel adder (74283),
Carry look ahead adder (74182), BCD adder (8283), Comparator (7485),
decoders(74138, 7442), encoder (74148), multiplexer (74157).
4. SEQUENTIAL LOGIC
12
Hrs
NAND / NOR gate latch, clocked signals and clocked flip flops (S-C, J-K, and
D), J-K master-slave flip flop. Ripple (asynchronous) counters (mod 2N and
mod mod < 2N), IC asynchronous counters (7490, 7493), asynchronous down
counter, cascading of counters, presettable counter (74193). Analysis of
clocked sequential circuits, design of clocked sequential circuits, state
reduction, state assignment, flip flop excitation tables, design of
synchronous counters. Shift registers, universal shift register ((74194),
Ring counter, Johnson counter. Schmitt trigger, monostable multivibrator,
clock generator circuits.
5.
MEMORY DEVICES
12
Hrs
Terminology, memory operation, CPU - Memory connections,ROM and its
architecture, Types or ROMs - PROM, EPROM,EEPROM, CDROM, Flash memory. ROM
applications,Programmable Logic Devices. RAM and its architecture, SRAM,
DRAM - structure and operation ,read/write cycles, refreshing, technology.
Expanding word size and capacity. Special memory functions.
Text Books:
1.Morris Mano, Digital logic and Computer design, PHI 1998 (Chapters
3,4,5,6,and 7)
2.Tocci and Widmer, Digital Systems, Seventh edition, Prentice Hall 1998
(Chapters 5,7,and 11)
Reference Books:
1. Bartee, Computer architecture and Logic design, McGraw hill 1991 2.
Nasliclsky, Introduction to digital technology, John Wiley 3. Fletcher, An
Engineering approach to Digital design, PIll 1990
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EC
CSE 35 : ELECTRONIC CIRCUITS
Hours per week: 4
I.A Marks:25
Total Lecture Hours:48
Exam Marks:100
1. SPECIAL PURPOSE DIODES
2Hrs
LED ,7 segement display, Photodiode,Photo transistor,Opto couple,Schottky
diode,varactor,Varistor
2. FETs 4
Hrs
JFET, Biased JFET, ID Vs VDS and ID Vs VGS curves, JFET approximations,
Depletion mode.MOSFET, Enhancement mode MOSFET.
3. FET CIRCUITS
4
Hrs
Self bias of JFETs, graphical solution for self bias,transconductance, JFET
amplifiers, JFET analog switch depletion mode MOSFET amplifiers, enhancement
mode MOSFET applications-passive load switching, active load switching, CMOS
inverter,, VMOS transistor.
4. THYRISTORS
4 Hrs
Four layer diode,SCR,photo SCR,gate controlled switch,silicon controlled
switch ,Diac,Triac,UJT.
5. OPAMPs
12Hrs
Non inverting voltage feedback, open loop and closed loop voltage gains,
input and output impedance, benefits of negative feedback. Current boosters
for voltage amplifiers, voltage controlled current source, differential and
instrumentation amplifiers, active filters, automatic gain control. Diode
Circuits using OPAMPs - half wave rectifier, peak detector, positive
limiter, positive damper. Comparator Schmitt trigger
6. 555 TIMER
2Hrs
Block diagram, monostable operation, astable operation, voltage controlled
oscillator, ramp generator.
7. REGULATED POWER SUPPLY
6
Hrs
Voltage feedback regulation, current limiting, power supply characteristics,
3 terminal IC regulators, current boosters, switching regulators.
8. IC LOGIC FAMILIES
8 Hrs
IC terminology, TTL family, standard TTL characteristics, improved TTL
series, TTL loading and fanout, connecting TTL outputs together, tristate
TTL. CMOS logic, CMOS series characteristics, low voltage technology, TTL
driving CMOS, CMOS driving TTL.
9. INTERFACING WITH ANALOG WORLD
6
Hrs
D to A conversion - weighted resistor DAC, R/2R ladder DAC,DAC
specifications. A to D conversion - Digital ramp ADC, successive
approximation ADC, flash ADC. Digital voltmeter, Digital storage
oscilloscope.
Text Books:
1.A.P. Malvino, Electronic Principles. Fifth edition, Tata McGraw Hill
1998 (Ch. 5-3,4; 7-14; 13-1,2,3,4,5,6,7; 14-1,2,4,5,6,7,8; 15-1,2,3,4,5;
19-1,2,3,4; 20-5,6,7,8,9; 21-1,2,3; 22-9; 23-1,2,3,4,5,7;)
2.Tocci and Widmer, Digital Systems, Seventh edition, Prentice Hall 1998
(Chapters.8-1,2,3A,5,7,8,14,l5, 16,20,21;10-1,2,3A,8,9,ll,l2,14,17)
Reference Books.
1.Millman and Halkias, Integrated Electronics, McGraw Ilill
2.Nastielsky and Boylested, Electronic devices and circuit theory. Prentice
Hall
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CSI
36L DATA STRUCTURES LAB
Hours per week : 3
Exam Marks: 100
Sessional Marks : 25
Ia. Write a C program to demonstrate the working of a Stack of size N
using an array. The elements of the Stack may assumed to be of type Integer
or Real. The operations to be supported are:
1. PUSH
2.
POP
3. DISPLAY
The program should print appropriate messages for Stack Overflow, Stack
Underflow and Stack Empty. You may write seperate functions to detect these
cases.
lb. Write a C program to evaluate a valid Suffix expression using
Stack. Assume that the suffix expression is read as a single line consisting
of non-negative single digit operands and binary arithmetic operators. The
arithmetic operators allowed are +(ADD),
- (SUBTRACT),
*
(MULTIPLY), and
/ (DIVIDE).
2. Write a C program to convert and print a given valid fully
parenthesized Infix arithmetic expression to Suffix expression. The
expression consisting of single character (letter or digit) as operands and
+,-, *, / as operators. You may assume that only binary operators are
allowed in the expression.
3. Write a C program to convert and print a given valid fuIly
parenthesized Infix arithmetic expression to Prefix expression. The
expression consisting of single character (letter or digit) as operands and
+. -.*, / as operators. You may assume that the Infix string is read from
right to left and that the Prefix string is created from right to left.
4a. Write a C program to simulate the working of an ordinary Queue of
integers using an array. Provide the following operations: l.QINSERT 2.
QDELETE 3.QDISPLAY Write functions to check the Queue status - QEmpty, QFull.
4b. Write a program to design a Priority Queue which is maintained as
a set of Queues (assume a maximum of 3 Queues). The elements are inserted
based upon the given priority. For example (3, 34) will be inserted to 3rd
Queue with the elemental value 34. The deletion of an element is to be done
starting from the 1st Queue, if it is not empty. In case if it is empty, the
elements from the 2nd Queue will be deleted, and so on.
5. Write a C program to simulate the working of a CircuIar Queue of
names using an array. Provide the following operations:
1. CQINSERT 2. CQDELETE
3. CQDISPLAY
Write functions to check the Queue status - QEmpty, QFull.
6. Using Dynamic variables and Pointers, write a C program to
construct a Singly Linked List - consisting of the following informations in
each node:
Job_id (Integers ), Job_name ( Character Suing ) Job_desc (Character String)
The operations to be supported are:
1. LINSERT - Inserting in the front of the List.
2. LDELETE - Deleting a node based on Job_id.
3.LSEARCH - Searching a node based on Job_id
4. LDISPLAY - Displaying all the nodes in the List.
7. A deque is a list in which items can be added or deleted from either
end of the List. Implement the following C functions to simulate the working
of such a Deque of integers, using Pointers and Dynamic variables.
1. Remleft
4. InsertRight
2. RemRight 5.
Display.
3. InsertLeft
8. Write a C program, using Dynamic variables and Pointers, to
perform the following operations: 1. Construct two Ordered ( Ascending )
Singly Linked Lists. 2. Combine these two ordered lists into a single
ordered List.
9. Using the Circular Linked List Data St:ructure write a program in
C to Add two long positive integers. The Circular lists can have Header
nodes and the numbers are to be inputted in a normal way. Each node in the
list contains a single digit of the number.
10. Write a program in C using dynamic variables and pointers to
support the following operations on Doubly Linked List of integers.
1. Create a Doubly Linked list by adding each node at the front.
2. Insert a new node to the left of the node whose key value is read as an
input.
3. Delete all occurrences of a given key, if it is found,otherwise display
appropriate message.
4. Display the contents of the List
11. Write a C program to implement an Ascending Priority Queue
(assume integer data type) as a Binary Search Tree. The program should
support the following operations:
1. PqInsert
2. PqminDelete
Preorder
and Postorder-to display tile elements in the Tree.
12. Using Pointers and Dynamic variables, Construct a Binary Search
Tree (BST) of integers. Write C functions to do the following:
1. Given a key, perform a search in the BST. If the key is found then
display "Key Found", else insert the key in BST.
2. While constructing the BST, do not add any duplicates.
3. Display the Tree using any one of the traversal Methods.
13. Write a C program to evaluate a given expression (the operands of
the expression may all be assumed as single character integer variables, the
values of which may be obtained from the user separately) using an
Expression Tree.
14. Write a C program to construct a Multilinked representation of a
Sparse Matrix. Assume that the Matrix is of dimension M x N, where M is tile
number of rows and N is tile number of columns. Using the Multilinked
representation , write a function to add two Sparse Matrices.
15a. Write a C program to sort a list of N elements of integer type
using the Quick Sort Algorithm.
15b. Write C program to simulate the working of Towers of Hanoi
problem for n disks. Print the number of moves taken by your program.
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LOGIC DESIGN
LAB
Hours per week : 3
Exam Marks: 100
Sessional Marks : 25
Note: General purpose Digital Trainer kit is to be used. Kits meant
for only specific experiments should not be used. Experiments could be
conducted using ICs of any logic family
1.Design a Half adder and a Full adder using NAND gates only. Cascade
them to implement a 2 bit binary adder.
2.Design and implement Excess-3 to BCD code converter using logic
gates. (Choice of Logic gates left to the student)
3.Design and implement using NAND gates:
a. 4:1 multiplexer
b. 2:4 decoder
4.Design and implement the following using 4-bit adder chip and
gates.
a. Excess-3 to BCD code converter
b. BCD to Excess-3 code converter
5.Design and implement a full adder using a multiplexer. Also
implement a multiplexer tree using 3 multiplexers.
6.Design and implement using decoder and other gates
g. Full adder
h. Full subtractor.
7.Design and implement a 3 variable Boolean SOP expression using 2
numbers of 4:1 multiplexer IC.
8.Design and implement a 3 stage asynchronous counter using J-K flip
flops to
count down from 7 to n (n > 0). Display result on discrete LEDs and the
waveform on CR0.
9.Design and implement asynchronous counter using a Decade counter IC to
count up from 0 to n (n <9). Display count value on 7 segment LED display
using BCD to 7 segment code converter IC.
10.Design and implement to display result suitably: k. Asynchronous
counter using 4 bit binary counter IC to count up from 0 ton (n <=15). I.
An asynchronous counter to count up to FFH using 2 stages of such an IC.
11. Design and implement Mod n (n <8) synchronous counter using
flip flops. Display result suitably.
12.Design and implement a 3-stage up/down counter that count. from a
preset value using Decade presettable counter ICs Display result suitably.
13. Design and implement using 4-bit shift register IC: n. Johnson
counter o. Ring counter .
14.Design and implement the following: a. Oscillator for a given
frequency using Schmitt trigger inverter and RC components. b. Crystal
controlled clock using CMOS inverters.
15.Design and implement a monostable multivibrator to generate pulse
of given duration using a non-retriggerable
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EC
CSE 38L: ELECTRONIC CIRCUITS LABORATORY
Hours per week::3
Exam marks: 100
Sessional Marks: 25
1. Diode characteristics. Half wave and full wave rectifiers.
Calculation of Average value, efficiency
2.Design OPAMP circuits to work as:
c.inverting amplifier
d.non-inverting amplifier
e .voltage follower.
3.FET characteristics and determination of FET parameters
4.Design OPAMP circuits to wok as:
e.half wave rectifier f.peak detector g.positive damper.
5.Design of OPAMP Schmitt trigger for given UTP and LTP and use it to
convert sine wave to square wave.
6.Design of OPAMP circuit to provide required current boost to the
voltage amplifier 7.Design of OPAMP circuit to work as voltage
controlled current source.
8.Design of astable multivibrator for a given frequency using 555
9.Application of 555 as a voltage controlled oscillator
10.Application of 555 as a ramp generator
11. Design of Voltage series regulator using Zener diode and a
transistor and to measure load regulation.
12.Design of a +8V regulator using +5V 3-terminal IC regulator and to
measure its load regulation.
13.Design of a current booster for 3-terminal IC regulator using
outboard transistor to produce load current of 5 Amperes.
14.Design of4 bit R-2R ladder DAC using OPAMP
15.Design of a digital ramp ADC.
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